Method of forming a trench for use in manufacturing a semiconductor device

ABSTRACT

A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This is a divisional of and a claim of priority is made to U.S.non-provisional application Ser. No. 10/673,873, filed Sep. 30, 2003,which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of forming a trench and to amethod of forming a semiconductor device having a trench.

2. Description of the Related Art

For some time now, semiconductor devices have been employed in mostelectronic devices including information processing apparatuses and homeappliances. Current demands for information processing apparatus, suchas computers, require that the apparatus posses a large processingcapacity and a high processing speed. Thus, semiconductor devices of theinformation processing apparatus must also have a high response speedand a large storage capacity. This is achieved through the integrationof the semiconductor device.

In general, the capacity of random access memory (RAM) chips has beenimproving according to Moores' law. Moore's law, postulated fromempirical data, indicates that the storage capacity of memory chips hasincreased by a factor of four every three years. This increase has beenaccomplished through a combination of reducing the size of semiconductordevices installed on the chip, and increasing the length of the chipaccordingly. The smaller the semiconductor device installed on thesilicon chip becomes, the finer the interconnect lines of thesemiconductor device must become. However, the signals running throughthe interconnect lines may interfere with each other when theinterconnect lines are arranged close to one another. In fact, delays inthe device will be caused by the interference when the spacing of theinterconnect lines is below a predetermined value. The specificresistance of the metal used for forming the interconnect lines must bereduced in this situation if a high processing speed of thesemiconductor devices is to be maintained.

Until recently, the interconnect lines of the semiconductor device wereformed using aluminum (Al) or an aluminum alloy having a specificresistance of approximately 2.66 μΩ·cm. However, in 1998, InternationalBusiness Machine Co. disclosed a method for forming an interconnect linewith copper (Cu). Moreover, since then, various researchers haveimproved upon the method of forming interconnect lines or wiring usingcopper. In particular, a damascene process was developed in order toform copper interconnection lines or copper wiring. More specifically, adual damascene process is often advantageously employed to form metalwiring and a contact all at once.

Recently, the damascene process for forming metal wiring of asemiconductor device or a bottom electrode of a capacitor has beenpreceded by etching an insulation layer to form a trench having apredetermined dimension in the insulation layer, wherein the damasceneprocess entails forming a copper film in the trench using electroplatingand chemical mechanical polishing (CMP) techniques. U.S. Pat. No.6,259,128 (issued to Douglas R. Robert et al.), Korean Patent Laid-OpenPublication No. 2003-10507, and Korean Patent Laid-Open Publication No.2003-2803 all disclose such methods of forming an insulation layer, atrench, a metal wiring and a capacitor.

FIGS. 1A and 1B illustrate a conventional method of forming a trench.Referring to FIG. 1A, an insulation layer 15 comprising an oxide ornitride is formed on a semiconductor substrate 10 such as a siliconwafer. A photoresist film (not shown) is then formed on the insulationlayer 15. The photoresist film is exposed and developed to form aphotoresist pattern 20 on the insulation layer 15. The photoresistpattern 20 is used as an etching mask during an etching process forforming the trench. Accordingly, the photoresist pattern 20 should havea height h and a width w sufficient for forming a trench having adesired width and depth. If the height of the photoresist pattern 20 istoo small, the photoresist 20 may be completely consumed before thetrench is not completely formed in the insulation film 15 during theetching process. In addition, the photoresist pattern 20 should have arelatively small width w because the trench becomes too narrow when thephotoresist pattern 20 is too wide.

Generally, the photoresist pattern 20 on the insulation layer 15 shouldhave an aspect ratio (a ratio of the height h relative to the width w)of more than about 3, as shown in FIG. 1A, for a satisfactory trench tobe formed by etching the insulation layer 15 using the photoresistpattern 20 as an etching mask. However, as shown in FIG. 1B, thephotoresist pattern 20 has an unstable structure when the photoresistpattern 20 has an aspect ratio of about 3− so much so that thephotoresist pattern 20 may collapse on the insulation film 15. If anattempt to solve this problem is made by augmenting the width of thephotoresist pattern 20, the width of the trench becomes too narrow (inan inversely proportional relation). Hence, copper (Cu) wiring may notbe formed in the trench to a desired dimension by the damascene processbecause of limitations that the photoresist pattern 20 imposes on thedimensioning of the trench. Additionally, the trench may not be formedin the insulation layer 15 at all or the trench may not have accuratedimensions when the etching process for forming the trench is performedusing a mask as a photoresist pattern 20 that has collapsed on theinsulation layer 15. In this case, a defective semiconductor device maybe produced, i.e., the yield of the semiconductor device manufacturingprocess is reduced. Furthermore, striations may be formed on theinsulation layer 15 or on the metal wiring when a successivemanufacturing process is performed while the photoresist pattern 20 iscollapsed. In this case, a fatal manufacturing error may occur duringthe next manufacturing process.

SUMMARY OF THE INVENTION

One feature of the present invention is to provide a reliable methodcapable of yielding trenches having precise dimensions for use in themanufacturing of semiconductor devices.

Another feature of the present invention is to provide a method offorming a conductive pattern having a desired dimension in themanufacturing of semiconductor devices.

Still another feature of the present invention is to provide a method ofmanufacturing a semiconductor device including metal wiring or aconductive pattern having very precise dimensions.

According to one aspect of the present invention, an insulation film isformed on a substrate, a photoresist pattern is formed on the insulationfilm, and two distinct etching processes are then carried out. The firstetching process is performed to form an initial trench in the insulationfilm using the photoresist pattern as a mask. The second etching processis subsequently executed to enlarge the initial trench. The insulationfilm may comprise an oxide, a fluoride or a nitride film. The secondetching process is performed using an etching solution includinghydrogen fluoride, ammonium fluoride, hydrogen peroxide and deionizedwater when the insulation film is an oxide or a fluoride film.Otherwise, the second etching process is performed using an etchingsolution including hydrogen fluoride, phosphoric acid and deionizedwater when the insulation film is a nitride film. The etching solutionmay further including an antioxidant such as benzo triazole to prevent ametal film subsequently formed in the enlarged trench from oxidizing.

According to another aspect of the present invention, conductivematerial is deposited in the enlarged trench to thereby form aconductive pattern having dimensions corresponding to those of theenlarged trench.

According to still another aspect of the present invention, aphotoresist pattern is formed on a substrate, and the substrate is thensubjected to two distinct etching processes. In a first etching process,an initial trench is formed in the substrate using the photoresistpattern as a mask. The initial trench is then enlarged by a secondetching process. Finally, an oxide film is formed to fill the enlargedtrench. The second etching process may be either a wet bench process inwhich the substrate is immersed in an etching solution or a single spinstation or a cylindrical spin station process in which an etchingsolution is sprayed on one or more substrates while the substrates arerotated.

According to yet another aspect of the present invention, two distinctetching processes are used to form a dual damascene structure of asemiconductor device. First, a first insulation film is formed on asubstrate and a first conductive pattern is formed in the insulationfilm. At least one etch stop layer and at least one second insulationfilm are then subsequently formed on the first insulation film. Next, afirst photoresist pattern is formed on the second insulation film.Subsequently, the etch stop layer and the second insulation film areetched using the first photoresist pattern as a mask to thereby forminga via hole that exposes the first conductive pattern. The firstphotoresist pattern is then removed. A second photoresist pattern isformed on the second insulation film after the first photoresist patternhas been removed, and an initial trench is formed in alignment with thevia hole by etching the etch stop layer and the second insulation filmusing the second photoresist pattern as a mask. The initial trench isthen enlarged by etching the second insulation film. Finally, conductivematerial is deposited over the structure to form a second conductivepattern in the via hole and a third conductive pattern in the enlargedtrench, respectively.

According to the present invention, the initial trench can be formedusing a first etching process in which a photoresist pattern having astable structure is used as an etching mask. Then, the initial trench isenlarged by performing the second etching process. The second etchingprocess is performed using an etching solution having a compositiondeveloped in accordance with the composition of the layer of material inwhich the initial trench is formed. Therefore, the final trench hasprecise dimensions. Accordingly, the patterned structure that is formedby filling the trench, e.g. a metal wiring, an oxide layer, or aconductive pattern, will also have precise dimensions.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of the present invention willbecome more apparent from the following detailed description of thepreferred embodiments thereof made with reference to the accompanyingdrawings, in which:

FIGS. 1A and 1B are cross-sectional views of a semiconductor substrateillustrating a conventional method of forming a trench;

FIGS. 2A to 2C are cross-sectional views of a semiconductor substrateillustrating one embodiment of a method of forming a trench according tothe present invention;

FIGS. 3A to 3D are cross-sectional views of a semiconductor substrateillustrating another embodiment of a method forming a trench accordingto the present invention;

FIGS. 4A to 4C are cross-sectional views of a semiconductor substrateillustrating one embodiment of a method of forming a conductive patternaccording to the present invention; and

FIGS. 5A to 5E are cross-sectional views of a semiconductor substrateillustrating one embodiment of a method of forming a semiconductordevice according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention will be described indetail hereinafter with reference to the accompanying drawings. Likereference numerals designate similar or identical elements throughoutthe drawings.

Referring to FIG. 2A, an insulation layer 55 is formed on asemiconductor substrate 50, having transistor structures thereon (notshown), using a thermal oxidation process or a chemical vapor deposition(CVD) process. The insulation layer 55 comprises an oxide, a nitride ora fluoride. In particular, the insulation layer 55 may including anoxide such as a middle temperature oxide (MTO), tetraethylortho-silicate (TEOS), boro-phosphor silicate glass (BPSG) or undopedsilicate glass (USG). In addition, the insulation layer 55 may comprisefluorinated silicate glass (FSG) or silicon oxyfluoride (SiOF).Furthermore, the insulation layer 55 may include a nitride such assilicon nitride (Si_(x)N_(y)) or silicon oxynitride (SiON). In any case,the insulation layer 55 covers the transistor structures on thesemiconductor substrate 50.

After a photoresist film (not shown) is formed on the insulation layer55, the photoresist film is developed and exposed to form a photoresistpattern 60. In this case, the photoresist pattern 60 has an aspect ratiofar less than that of the prior art. That is, the photoresist pattern 60has a width w′ greater than that of the photoresist pattern shown inFIG. 1A while the photoresist pattern 60 has a height h′ that is lessthan that of the conventional photoresist pattern shown in FIG. 1A. Thephotoresist pattern 60 of the present invention has a stable structurebecause the photoresist pattern 60 has a small aspect ratio. As aresult, the photoresist pattern 60 does not collapse on the insulationlayer 55.

Referring to FIG. 2B, the insulation layer 55 is etched using a firstetching solution and the photoresist pattern 60 as a mask to form atrench 65 (an initial trench) in the insulation layer 55. The firstwidth w₁ and the first depth d₁ of the trench 65 depend on the dimensionof the metal wiring to be formed in the trench 65. For example, thetrench 65 has a first width w₁ of approximately 1,000 to 1,200 Å whenthe line width of the metal wiring is to be about 1,500 to about 2,400Å. In addition, the trench 65 has the first depth d₁ based on thethickness of the insulation film 55.

Then, a second etching process is performed using a second etchingsolution, as shown by arrows in FIG. 2B. The second etching process maybe a wet bench process, a single spin station process or a chemical spinstation process. The wet bench process comprises immersing thesemiconductor substrate 50 into a bath containing the second etchingsolution. About 25 to about 50 substrates can be simultaneously etchedin the bath. On the other hand, the single spin station processcomprises mounting the semiconductor substrate 50 on a rotatable chuck,and spraying the second etching solution onto the insulation layer 55while the substrate 50 is being rotated by the chuck. Still further, thechemical spin station process may comprise inserting about 25 to about50 substrates into a cylindrical station, and then spraying the secondetching solution onto the insulation layer 55 while the substrates arerotated in the cylindrical station.

In the present embodiment, when the insulation film 55 includes an oxideor a fluoride, the second etching solution includes fluorine.Preferably, the second etching solution includes hydrogen fluoride (HF),ammonium fluoride (NH₄F), hydrogen peroxide (H₂O₂) and deionized water(H₂O). In this case, the volumetric ratio between the hydrogen fluorideand the ammonium fluoride is approximately 1:1 to 1:10, and thevolumetric ratio between the hydrogen fluoride and the hydrogen peroxideis approximately 1:1 to 1:10. In addition, the volumetric ratio betweenthe hydrogen fluoride and the deionized water is approximately 1:100 to1:500. The second etching solution having the composition describedabove can etch the insulation film 55 at a rate of close to 40 to 60Å/minute.

On the other hand, the second etching solution includes phosphoric acid(H₃PO₄) and deionized water when the insulation film 55 comprises anitride. When the metal wiring to be formed in the trench 65 is ofcopper (Cu), the second etching solution includes an antioxidant, suchas benzo triazole (BTA), to prevent the metal wiring from oxidizing.

Referring to FIG. 2C, the second etching process enlarges the trench 65.That is, the trench 65 has a second width w₂ wider than the first widthw₁ and a second depth d₂ substantially identical to the first depth d₁.For example, when the trench 65 has the first width w₁ of about 1,000 toabout 1,200 Å, the second etching process is performed for about 6 toabout 10 minutes. At the end of the second etching process, the trench65 has the second width w₂ of about 1,5000 to about 2,400 Å because theetching rate of the insulation layer 55 is about 40 to about 60Å/minute. The second depth d₂ of the trench 65 is substantiallyidentical to the first depth d₁ because the upper portion of theinsulation layer 55 is etched along with a lower portion of theinsulation layer 55 that defines the bottom of the trench 65.

Therefore, a metal wiring having a desired line width can be formed inthe trench 65 using a damascene process because the trench 65 isprovided with precise dimensions through the first and second etchingprocesses.

FIGS. 3A to 3D illustrates another embodiment of a method of forming atrench according to the present invention.

Referring to FIG. 3A, a trench 90 is formed in a semiconductor substrate80, comprising silicon, to define a cell region and a peripheral circuitregion. More specifically, a photoresist film (not shown) is formed onthe substrate 80. The photoresist film is then exposed and developed toform a photoresist pattern 85. The substrate 80 is etched (a firstetching process) using the photoresist pattern 85 as a mask, therebyforming the trench 90 in the substrate 80. Referring to FIG. 3B, thetrench 90 has a first width w₁ and a first depth d₁ once the firstetching process is completed. The first width w₁ of the trench 90 isnarrower than an isolation film to be formed later in the trench 90.

The trench 90 is enlarged using a second etching process. As describedabove, the second etching process may be a wet bench process, a singlespin station process or a chemical spin station process.

In this embodiment, the second etching process is performed using anetching solution including hydrogen fluoride, nitric acid (HNO₃) anddeionized water in order to etch the semiconductor substrate 80 in whichthe trench 90 has been formed. The substrate 80 is etched at an etchingrate of about 40 to 60 Å/minute. The duration of the second etchingprocess can be selected so that the isolation film to be formed in thetrench 90 will have the desired dimensions.

Referring to FIG. 3C, after the second etching process has performed,the trench 90 has a second width w₂ greater than the first width w₁ anda second depth d₂ substantially identical to the first depth d₁. Forexample, when the trench 90 has a first width w₁ of about 1,000 to about2,000 Å, the second etching process can be performed for about 5 to 10minutes to form the trench 90 having the second width w₂ ofapproximately 2,200 to 3,200 Å (based on the etching rate of the secondetching process of about 40 to about 60 Å/minute). Again, the seconddepth d₂ of the trench 90 is substantially identical to the first depthd₁ because the upper portion of the substrate 80 is etched along with alower portion defining the bottom of the trench 90 during the secondetching process.

Referring to FIG. 3D, an initial oxide film (not shown) is formed on thesubstrate 80 using a chemical vapor deposition (CVD) process to fill thetrench 90. The initial oxide film is etched using an etch-back processor a chemical mechanical polishing (CMP) process so as to form anisolation film 95 in the trench 90. The isolation film 95 demarcates theactive region and the peripheral circuit region on the semiconductorsubstrate 80.

FIGS. 4A to 4C illustrate a method of forming a conductive patternaccording to the present invention. Referring to FIG. 4A, an isolationfilm 105 is formed on a semiconductor substrate 100 having transistorstructures (not shown) formed thereon using a CVD process. Theinsulation film 105 includes an oxide, a nitride or a fluoride. In thiscase, the insulation film 105 includes an oxide such as MTO, TEOS, BPSGor USG. Additionally, the insulation film 105 includes a fluoride suchas FSG or silicon oxyfluoride or the insulation film 105 includes anitride such as silicon nitride or silicon oxynitride. The insulationfilm 105 covers the transistor structures formed on the semiconductorsubstrate 100. Alternatively, an upper portion of the insulation film105 can be planarized using a CMP process or an etch-back process.

After a photoresist film (not shown) is formed on the insulation film105 using a spin coating process, the photoresist film is patterned toform a photoresist pattern 110 using an exposure process and adeveloping process.

The insulation film 105 is etched partially using the photoresistpattern 110 as a mask to form a trench 115 having a first width w₁ onthe insulation film 105. That is, the trench 115 first having the firstwidth w is formed using a first etching solution by a first etchingprocess. When a metal wiring or a conductive pattern formed in thetrench 115 has a width of about 1,500 to about 2,400 Å, the first widthw₁ of the trench 115 is about 1,000 to about 2,000 Å. The metal wiringincludes a bit line and the conductive pattern includes a bottomelectrode of a capacitor, a contact or a pad of a semiconductor device.The conductive pattern or the metal wiring includes copper (Cu),aluminum (Al) or tungsten (W).

The present embodiment, because the trench 115 has an extended widthusing a successive process for extending the width of the trench 115,the photoresist pattern 110 formed on the insulation film 105 has anaspect ratio greatly smaller than that of the conventional photoresistpattern as described above. Thus, the photoresist pattern 110 has astable structure to prevent the photoresist pattern 110 from fallingdown on the insulation film 105.

Referring to FIG. 4B, the resultant structure including the insulationfilm 105 having the trench 115 therein is etched using a second etchingsolution. This second etching process may be a wet bench process, asingle spin station process or a chemical spin station process. Thesecond etching solution has a composition based on the composition ofthe insulation film 105. For instance, the second etching solutionincludes hydrogen fluoride, ammonium fluoride, hydrogen peroxide anddeionized water when the insulation film 105 includes oxide of fluoride.Also, the second etching solution includes hydrogen fluoride, phosphoricacid and deionized water when the insulation film 105 includes anitride.

Alternatively, when the conductive pattern including copper is formed inthe trench 115, the second etching solution includes an antioxidant suchas BTA in order to prevent the conductive pattern from oxidizing. Theantioxidant forms an insoluble film on the surface of the trench 115 toprotect the conductive pattern.

In any case, the width of the trench 115 is increased so that the trench115 has a second width w₂. More specifically, the second etchingsolution etches the insulation film 105 at a rate of about 40 to about60 Å/minute. Therefore, when the first width w₁ of the trench 115 isabout 1,000 to about 1,200 Å, and the second etching process isperformed about 6 to about 10 minutes, the second width w₂ of the trench115 becomes about 1,500 to about 2,400 Å. Hence, the trench 115 hasdimensions that will facilitate the forming of a conductive patternhaving desired dimensions in the trench 115.

Referring to FIG.4C, a conductive film (not shown) is formed on theinsulation film 105 to fill the trench 115 having the second width w₂.The conductive film is formed using a sputtering process, a CVD processor an electroplating process. The conductive film includes copper,tungsten, aluminum, titanium or titanium nitride.

A portion of the conductive film on the insulation film 105 is removedusing an etch-back process or a CMP process so that a conductive pattern120 is formed in the trench 115. The conductive pattern 120 may serve asa metal wiring, an electrode, a contact or a pad of a semiconductordevice.

FIGS. 5A to 5E illustrate a method of forming a semiconductor deviceaccording to the present invention. In this embodiment, themanufacturing of the semiconductor device employs a dual damasceneprocess.

In general, a dual damascene structure of a semiconductor deviceincludes a via hole structure and a trench structure. A contact for anelectrical connection between an upper conductive film and a lowerconductive film is formed in the via hole, and a metal wiring is formedin the trench. To form the dual damascene structure, the trench can beformed in an insulation film at the via hole. Additionally, the via holecan be formed after the trench is formed in the insulation film.Furthermore, the via hole and the trench can be simultaneously formedthrough and in the insulation film. In the present embodiment, a trenchis formed at a via hole extending through an insulation film.

Referring to FIG. 5A, an isolation film (not shown) is formed on asemiconductor substrate 150 in order to define a cell area and aperipheral circuit area on the substrate 150. A transistor structure(not shown) is formed on the cell area of the substrate 150. In thiscase, an isolation region can be manufactured according to the methoddescribed with references to FIGS. 3A to 3D. That is, a first trench(not shown) is formed in the substrate 150, and then the width of thefirst trench is enlarged using an etching process. Then, the firsttrench is filled with an oxide film to form an isolation film forisolating the circuit area from the peripheral area. Alternatively, theisolation film can be formed using a thermal oxidation process such as alocal oxidation of silicon (LOCOS) process or a shallow trench isolation(STI) process.

A first insulation film 155 including oxide, fluoride or nitride is thenformed on the semiconductor substrate 150. Subsequently, a part of thefirst insulation film 155 is etched using a photolithography process toform a second trench 160 in the first insulation film 155.

The second trench 160 is enlarged by using an etching solution that hasa composition that is based on the composition of the first insulationfilm 155 (i.e., by using a second etching process as described above).As a result, the width of the second trench 160 is increased.

Referring to FIG. 5B, a first conductive film (not shown) is formed onthe first insulation film 105 using a sputtering process, a CVD processor an electroplating process to thereby fill the second trench 160. Thefirst conductive film is etched using an etch-back process or a CMPprocess to form a first conductive pattern 165 in the second trench 160.At this time, an upper surface of the first conductive film 165 isexposed.

A first etch stop layer 170 is formed on the first insulation film 155including over the first conductive pattern 165. The first etch stoplayer 170 includes a non-oxide material such as a nitride or acarbon-based compound such as silicon carbide (SiC). The first etch stoplayer 170 protects the first conductive pattern 165 during subsequentprocesses used to form a third trench and a via hole (described in moredetail below).

A second insulation film 175 including an oxide, a fluoride or a nitrideis formed on the first etch stop layer 170. The material of the secondinsulation film 175 may be identical to or different from that of thefirst insulation film 155. The via hole will be formed through the firstetch stop layer 170 and the second insulation film 175 in order tofacilitate the forming of an electrical contact connected to the firstconductive pattern 165. The second insulation film 175 electricallyinsulates contacts formed in adjacent via holes from one another.

Referring to FIG. 5C, a second etch stop layer 180 and a thirdinsulation film 185 are successively formed on the second insulationfilm 175. The second etch stop layer 180 includes a non-oxide materialsuch as a nitride or a carbon-based compound like f silicon carbide, andthe third insulation film 185 includes an oxide. A third trench will beformed on the third insulation film 185, and the metal wiring will beformed in the third trench. The third insulation film 185 electricallyinsulates adjacent portions of the metal wiring formed in the thirdtrenches, respectively. The second etch stop layer 180 provides an endpoint of the process in which the third insulation film 185 is etched toform the third trench. However, the second etch stop layer 180 cannot beomitted.

A capping layer 190 including an oxide or a fluoride is formed on thethird insulation film 185. For example, the capping layer 190 includesundoped silicon oxide (SiO₂), silicon oxide formed using a plasmaenhanced CVD process, USG, or TEOS. Alternatively, the capping layer 190includes silicon oxyfluoride (SiOF).

A first photoresist film (not shown) is then formed on the capping layer190. Subsequently, the first photoresist film is exposed and developedto form a first photoresist pattern 195 for use in forming the via hole200. That is, the capping layer 190, the third insulation film 185, thesecond etch stop layer 180 and the second insulation film 175 aresuccessively etched using the first photoresist pattern 195 as anetching mask so that the via hole 200 exposes a portion of the firstetch stop layer 170.

Referring to FIG. 5D, the photoresist pattern 195 is removed using anashing process and a stripping process. Then, a second photoresist film(not shown) is formed on the capping layer 190. The second photoresistfilm is exposed and then developed to form a second photoresist pattern205 that exposes the via hole 200 and a portion of the capping layer 190around the via hole 200.

The capping layer 190, the third insulation film 185, the second etchstop layer 180 and the first etch stop layer 170 are etched using thesecond photoresist pattern 205 as an etching mask. Thus, a third trench210 extending from the via hole 200 is formed in the second etch stoplayer 180 to the capping layer 190. The third trench 210 is wider thanthe view hole 200. Note, the first conductive pattern 165 is exposedduring the forming of the third trench 210.

Referring to FIG. 5E, the second photoresist pattern 200 is removed, anda second etching process is performed using an etching solution having acomposition based on the compositions of the capping layer 190, thethird insulation film 185 and the second etch stop layer 180. As aresult, the width of third trench 210 is increased. In this case, thecapping layer 190, the third insulation film 185 and the second etchstop layer 180 are simultaneously etched. In addition, the secondinsulation film 175 can be simultaneously etched with the capping layer190, the third insulation film 185 and the second etch stop layer 180.Alternatively, the second insulation film 175 can be etched after thecapping layer 190, the third insulation film 185 and the second etchstop layer 180 are etched. In either case, the diameter of the via hole200 can be increased.

A second conductive film (not shown) is formed on the capping layer 190using a sputtering process, a CVD process or an electroplating processto fill the third trench 210 and the via hole 200. The second conductivefilm includes copper, aluminum, tungsten or titanium. Then, the secondconductive film and the capping layer 190 are etched using an etch-backprocess or a CMP process until the third insulation film 185 is exposed.Hence, a second conductive pattern 215 and a third conductive pattern220 are simultaneously formed in the third trench 210 and in the viahole 200, respectively. That is, a dual damascene structure is formed.The second conductive pattern 215 serves as a metal wiring such as bitline of the semiconductor device, and the third conductive pattern 220serves as a contact for connecting metal wirings.

According to the present invention, a trench is formed in asemiconductor substrate or an insulation film using a photoresistpattern having a stable structure as an etching mask. Then, a secondetching process is performed using an etching solution tailored to thecomposition of the semiconductor substrate or the insulation film towiden the trench. Therefore, a metal wiring, an isolation film or acontact having precise and desired dimensions can be formed in thetrench. Thus, the present invention is not subject to the problems ofthe prior art of producing semiconductor devices that fail due to thecollapse of the photoresist pattern during the manufacturing process. Inother words, the present invention produces reliable semiconductordevices at a sustainable high yield.

Finally, although the present invention has been described above inconnection with the preferred embodiments thereof, various modificationsthereto will become obvious to those of ordinary skill in the art. It istherefore to be understood that the preferred embodiments of the presentinvention may be modified or changed disclosed without departing fromthe true scope and spirit of the invention as set out in the appendedclaims.

1. A method of forming an isolation film for use in manufacturing of asemiconductor device, said method comprising: forming a photoresistpattern on a substrate; performing a first etching process comprisingetching the substrate using the photoresist pattern as a mask to form aninitial trench in the substrate; subsequently performing a secondetching process that is distinct from said first etching process, saidsecond etching process comprising etching the substrate in which theinitial trench is already formed to thereby enlarge the initial trench;and subsequently forming an oxide film that fills the enlarged trench.2. The method of claim 1, wherein said forming of the oxide filmcomprises forming an initial oxide film on the substrate in and aroundthe enlarged trench, and subsequently removing a portion of the initialoxide film from a top surface of the substrate while leave anotherportion of the initial oxide film in the enlarged trench.
 3. The methodof claim 1, wherein said second etching process comprises wetting thesubstrate with an etching solution that etches silicon.
 4. The method ofclaim 2, wherein the etching solution includes hydrogen fluoride, nitricacid (HNO₃) and deionized water.
 5. A method for manufacturing asemiconductor device comprising: forming a first insulation film on asubstrate; forming a first conductive pattern in the insulation film;forming at least one etch stop layer and at least one second insulationfilm in the foregoing sequence on the first insulation film; forming afirst photoresist pattern on the second insulation film; etching theetch stop layer and the second insulation film using the firstphotoresist pattern as a mask to form a via hole that exposes the firstconductive pattern by removing the first photoresist pattern;subsequently forming a second photoresist pattern on the secondinsulation film, the second photoresist pattern having an openingaligned with the via hole; etching the stop layer and the secondinsulation film using the second photoresist pattern as a mask tothereby form an initial trench aligned with the via hole; subsequentlyetching the second insulation film to enlarge the initial trench; anddepositing a conductive material in the via hole and in the enlargedtrench to thereby form a second conductive pattern and a thirdconductive pattern in the via hole and in the enlarged trench,respectively.